IBM has unveiled a new chip design that it claims could enable manufacturers to cram 100 billion transistors onto a silicon chip the size of a fingernail.

The current industry-standard size for chips, measured in nanometres (a billionth of a metre and the size of a few atoms), is around 2 nanometres (nm). However, IBM says its new chip technology is the equivalent of roughly 0.7nm, potentially making it the world's first known chip technology below 1nm.

It will be several years before the chip technology could be ready for production. The firm claims that in tests, its prototype performed 50% better than its own 2nm chip and was 70% more energy efficient.

Jay Gambetta, director of IBM Research and IBM Fellow, described the NanoStack technology as a "landmark moment" for the future of chips. "With our new NanoStack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," he said.

Transistors are the building blocks of silicon chips, providing computing power for the world's electronics, including smartphones, games consoles, and laptops. They have also become crucial to the powerful computers housed in data centres, processing a range of everyday digital activities from streaming to online banking, and powering the generative AI boom.

The more transistors manufacturers can squeeze onto a chip, the more powerful the chip becomes. For decades, the number of transistors that can be put onto a chip has doubled every two years: a phenomenon known as Moore's Law. But with billions of transistors now on some chips, it is growing more difficult to sustain this pace of growth.

IBM's approach is to layer sheets of transistors on top of each other. Professor Alan Woodward, a computer scientist at Surrey University, compared it with building a big block of flats rather than houses in a city. "IBM's NanoStack is like proposing a 100-storey skyscraper," he said, adding that in his view, the firm's closest rivals such as Samsung and Intel are closer to 30-50 storey buildings with their own 3D chip work.

The challenges facing 3D chip designers include heat: the transistors can get hot as they work and heat rises. Additionally, when the layers between them are too thin, sometimes this prevents them from switching off when they're supposed to, and this stops the chip from working. "I think it's fair to say IBM's proposals are the most ambitious," said Prof Woodward.

Source: www.bbc.co.uk